Neural networks speed up 3nm nanosheet SPICE simulation up to 8x

Researchers at TU Munich built neural-network transistor models for 3nm nanosheets and used them to characterize a standard cell library. Delay error stayed under 0.11% and total power error at 0.76%, while simulation time dropped by up to 8x versus the BSIM-CMG compact model.

• NN model errors: under 0.11% for delay, 0.76% for power
• Standard cell library characterization up to 8x faster
• Models validated on analog and digital circuits
• Paper published on arXiv in October 2026