Intel's EMIB and Foveros advanced packaging roadmaps analyzed

Intel's EMIB and Foveros packaging roadmaps show FLI bump pitch shrinking from 55 µm to 25 µm, bridge counts rising from 6 to 38+, and SiP size growing from 2 to 12 reticles. The goal is 24+ HBM stacks and a glass substrate by 2030.

• EMIB FLI bump pitch shrinks from 55 µm to 25 µm
• EMIB-T adds TSVs for vertical power delivery through the bridge
• SiP size grows from 2 to 12 reticles, bridges to 38+
• Glass substrate and 24+ HBM stacks targeted by 2030