Synopsys certifies A14 EDA flows with TSMC, tapes out 64G UCIe on 2nm and 3nm
Synopsys has certified its digital and analog EDA flows on TSMC's A14 process and completed 64G UCIe IP tape-outs on TSMC's 2nm and 3nm nodes. On N2P it reports IP for PCIe 7.0, HBM4, LPDDR6 and 224G Ethernet, plus co-design flows for integrated voltage regulators on CoWoS and photonic-electronic design for COUPE.
- A14 certification covers digital and analog flows from implementation to signoff
- 64G UCIe tape-outs completed on 2nm and 3nm with embedded DFT
- N2P IP milestones include PCIe 7.0, HBM4, LPDDR6 and 224G Ethernet
- 3DIC Compiler automates chiplet floorplanning on TSMC 3DFabric packaging
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