China builds working 3nm GAA transistors without EUV

IMECAS has developed an experimental process flow for stacked-nanosheet gate-all-around transistors using immersion DUV lithography and demonstrated functional devices. Ion/Ioff ratios reached 9.7×10⁵ and 7.6×10⁵, above the 5×10⁵ threshold, but critical geometry and a full 3nm manufacturing process remain undisclosed.

• IMECAS demonstrated working GAA transistors made with DUV lithography, no EUV
• Ion/Ioff ratios hit 9.7×10⁵ and 7.6×10⁵ versus the 5×10⁵ threshold
• Gate pitch, transistor and SRAM density were not disclosed
• A production-ready 3nm-class process is still far off