Self-aligned CFET could extend CMOS scaling beyond 10 Å

Semiverse Solutions modeled a self-aligned CFET architecture in SEMulator3D that vertically stacks NMOS and PMOS devices. It delivers a 0.0094 μm² SRAM bit cell — 52.7% smaller than N3 — and at least a 10 nm overlay window across critical contact layers.

• SRAM bit cell of 0.0094 μm²: 52.7% smaller than N3 and 19% smaller than A7 CFET
• Three self-aligned modules: buried power rail, contacts and TSV widen the overlay window
• At least 10 nm overlay window with no open or short failures
• Compatible with N3 specs: 42 nm CPP and 21 nm metal pitch