IBM details Nanostack transistor architecture and 0.7nm PDK plans

IBM is advancing its Nanostack architecture, which vertically stacks and staggers complementary transistors, introduced at its 0.7nm node in June 2026. It reports nearly twice the transistor density of its 2nm technology and projects up to 50% performance gains. An early process design kit with standard-cell libraries and an SRAM design is planned for Q1 2027.

• Nearly double the transistor density of IBM's earlier 2nm technology
• Projected up to 50% more performance or major efficiency gains
• About 100 billion transistors on a 150 mm² chip
• Early PDK with cell libraries and SRAM due in Q1 2027