SK hynix develops SSD controllers with hundreds of small H-TPU cores

SK hynix presented at ISOCC 2026 an SSD controller architecture that offloads read and write processing to hundreds of small H-TPU cores. Each core takes 4% of the area of an ARM Cortex-R8 core and about 2.5% of its power, freeing the main CPU for storage policy and error handling.

• H-TPUs use 4% of an ARM Cortex-R8 core's area and 2.5% of its power
• The cores handle read/write commands, metadata and buffer control
• The design will appear in AIN P, AIN B and AIN D SSD controllers
• Architecture targets PCIe 6, 7 and 8 with doubling speeds