SK Hynix unveils 3D Stacked DRAM bonded directly onto processor dies, targeting 2028

At SEDEX 2026 in Seoul, SK Hynix disclosed a 3D Stacked DRAM architecture that bonds DRAM dies directly onto processor dies via Through-Silicon Via interconnects, removing the silicon interposer used by current HBM. The company targets mass production in 2028 and is developing a 16-active-die configuration.

• DRAM bonds directly onto GPU/NPU dies via TSV, no 2.5D interposer
• Mass production targeted for 2028 with a 16-active-die configuration
• SK Hynix projects AI infrastructure demands to grow 19–20x by 2030
• HBF OCP specification aims for a complete standard in January 2027