imec details CFET integration modules and scalable standard cell architecture

imec presented two optimized CFET process modules: a backside contact and a gate-stack integration enabling multiple threshold voltages. It also introduced a scalable sequential CFET architecture with split-gate and common-gate options, extending the logic roadmap to the A3 node.

• CFET stacking pMOS and nMOS can shrink standard cells down to 3T
• Development follows two tracks: monolithic mCFET and sequential sCFET
• New split-gate sCFET architecture aids both logic and SRAM scaling
• Improved BEOL routability supports CFET standard cell scaling