RAPID enables row-parallel arithmetic computing inside DRAM

Researchers from Syracuse University, FAU and TU Dresden published RAPID, a processing-in-DRAM architecture that computes directly on row-parallel data. Two lightweight subarray extensions — migration and inversion cells — remove the costly data-layout transformations required by existing DRAM-PUM designs.

• RAPID adds migration and inversion cells to the DRAM subarray
• Computation runs on row-parallel, bit-parallel data in place
• CPU-compatible layouts are preserved, avoiding data reorganization
• Paper published on arXiv as arXiv:2610.02502