AMD details Epyc Venice: up to 256 cores and 1 GB of L3

AMD's whitepaper on Zen 6-based Epyc Venice reveals up to 256 cores, 16 channels of DDR5-8000/12800, 128 lanes of PCIe 6.0 and CXL 3.1 support. Performance-optimized parts ship in 2026, with the rest of the lineup following in 2027.

• SP7 platform: up to 256 cores, 16 DDR5 channels, 128 PCIe 6.0 lanes
• Memory bandwidth up to 1.6 TB/s, nearly 3x that of Turin
• Venice-X brings back 3D V-Cache: up to 1152 MB L3 per socket, 5.15 GHz
• Dense CCDs pack 32 cores and 128 MB L3, up to 1 GB L3 per chip