Validating PCIe 6.0 Connectivity In A 3D Multi-Die Test Chip

Synopsys demonstrated a test chip where PCIe 6.0 at 64 GT/s with PAM4 operates in a 3D architecture with vertically stacked dies. Over 8 lanes, up to 128 GB/s is achieved, and bit error margin exceeds standard requirements by several orders of magnitude.

• PCIe 6.0 speed — 64 GT/s, up to 128 GB/s over 8 lanes
• PHY implemented in 5-nm process with enhancements for 3D-IC
• BER margin exceeds PCIe 6.0 requirements by orders of magnitude
• Solution for AI accelerators, HPC, switches, and CXL systems