Intel CTO: chip output can double, but not 10x

Intel CTO Pushkar Ranade told the Dwarkesh Podcast that the industry lacks the tools to make 10 times more leading-edge wafers, with roughly 2x being the realistic ceiling. EUV lithography is the biggest bottleneck: ASML ships fewer than 100 machines a year, and tool orders take about 18 months to arrive.

• Ranade: leading-edge wafer output can grow about 2x, not 10x
• ASML makes fewer than 100 EUV scanners a year, shared by Intel, TSMC and memory makers
• About 80% of 18A tools can be reused for the 14A node
• Tools ordered today arrive in about 18 months, pushing deliveries into 2028