Former TSMC VP charts path past AI's memory wall with HBM and 3D stacking

Stanford professor and former TSMC VP H.-S. Philip Wong outlined how to break AI's memory wall: memory bandwidth is growing slower than processor performance, constraining AI chip efficiency. He points to HBM, optical links and 3D stacking as the way forward.

• Memory bandwidth lags processor performance, limiting AI chip efficiency
• Proposed fixes: HBM, optical interconnects and 3D stacking
• Author is H.-S. Philip Wong, Stanford professor and ex-TSMC VP