Huawei Claims LogicFolding Cuts Clock Buffers 50%, Expert Warns Heat Issue Persists

Huawei says its LogicFolding tech shortens interconnect length by 20%, critical paths by up to 70%, and clock buffers by around 50%, lowering power needs. Semiconductor expert @Taog_1575 argues the vertical stacking worsens heat dissipation, which is why Qualcomm and Apple show no interest in LogicFolding for mobile chips. He estimates Huawei may only match TSMC's N3E process by 2030.

• Huawei: LogicFolding cuts clock buffers 50% and critical paths up to 70%
• Expert: heat dissipation decay, similar to BSPDN thermal tax
• Qualcomm and Apple have no interest in LogicFolding for mobile chips
• Huawei may only reach TSMC N3E parity by 2030